(주)세미솔루션에 오신것을 환영합니다.

IC LEVEL ESD SOLUTION

(주)세미솔루션은 미국 GTL사와의 제휴를 통해 미국 특허의 Non-Snap back 방식의 ESD protection IP와 이를 이용한 ESD protection Design Service 및 Consulting을 제공하고 있습니다. GTL사의 ESD protection solution은 기존 ESD I/O protection 방식과는 근본적으로 차이가 있으며, IC 설계 단계부터 IC Core 내부의 전체적인 Power domain을 ESD에
효과적으로 대응할 수 있도록 solution을 제공하고 있습니다.
특히 Foundry 및 Process 호환성이 있어 용이하게 적용가능하며, 사전 Simulation을 통해 IC 제작을 하지않고도 ESD
특성을 미리 파악할수있는 것은 GTL사 ESD solution만의 특화된 장점입니다.

More aggressive processes, rules and designs cause ESD failure mechanisms that were not observed previously.
I/O ESD protection by foundry and I/O library vendors usually over-protects I/O, and allows core circuit failure.
There is no one ESD protection scheme or device that can protect all circuit from ESD damage
(no one-size-fits-all remedy !!)

In-depth coverage on complete spectrum of chip making
	- GTLeader's expertise covers complete spectrum of chip making; processes, modeling, simulution, reliability, circuit design, packaging, etc…. - GTLeader's ESD experts have fixed more than 300 designs from 0.35um to 0.13um technology node. - GTLeader has a whole chip level ESD protection solution as well as special and high speed I/O protection cells
Design review
	- GTLeader will review your design before tape-out to improve ESD performance. - GTLeader will provide ESD design rules and a super set of TSMC ESD design rules,coverign core circuit protection schemes as well as I/O - TLP test service for design and debugging
TLP Testing
	- GTLeader provides TLP testing for FA and design verification.

Device simulators like Medici(Pisces), Davinci, etc., have been used almost 20years to simulate a vaiety of effects, including latch-up and ESD. They are quite complicated to use, but provide good physics, including geometry effects. However, device simulators have their own set of problems, such as, run out of grid nodes quickly and 3D simulators are too slow.
Circuit simulators like Spice have been used, but not as successfully because they cannot deal very well with geometrical effects, and especially temperature coupling.

GTLeader in alliance with Sequoia Design Systems can provide accurate ESD/LU simulation to provide much
greater understanding of what is happening in the devices and circuits during failure. This insight is almost
impossible to obtain from experimental data alone.
GTLeader sratt have used simulation to predict failur mechanisms from 3um down to 90nm technologies.

Long testing due to ever increasing chip size, and repeated zapping to the same pin cause serious testing artifacts.
Current JEDEC spec and testing methodologies were developed some time ago. ESD testing labs interprete the JEDEC spec in their own way

ESD/LU testing without "side effects"
	- GTLeader provider optimized pin reduction method based on I/O ESD protection and power rail protection scheme analysis - Split test method to avoid charging/cumulative stres effects
Resident expertise on all required testing standards
	- ESDA/JEDEC standards: HBM, MM and CDM testing - ESDA standards: TLP, TLU - ESDA system level standard: calibration method - AEC & EIA/JEDEC standard: static and vectored LU - IEC 6000-4-2 system level (Human-Metal) standard - AEC automotive standard for HBM, MM and CDM
Guaranteed ESD testing
	- GTLeader will backup test result for you when your customer raises any question on testing that GTLeader has provided.

Application into Designs Case I : RF IC

2.5GHz RF IO with ESD cap. of 150fF. This design passed 5000V HBM, 300V MM, and 700V CDM.

Application into Designs Case II : Display Driver IC

ESD performance of GTL IP for high voltage LCD driver IC.Passed 4000V HBM, 300V MM

Application into Designs Case III : Timing Controller

LVDS power domain in TCON design with GTL ESD IP.This design passed 8000V HBM, 400V MM, and 700V CDM

Application into Designs Case III : Timing Controller

LVDS input pin in TCON design with GTL ESD IP.This design passed 8000V HBM, 400V MM, and 700V CDM.