| CPU |
FA626 , 500 MHz (max.), 32K I-cache/32K D-cache ( Provided by Faraday Technology ) |
| Memory Interface |
16-bit DDR2DDR2-400 SDRAM interface x3 |
| Shared asynchronous SRAM/ROM/Flash interface |
| NAND Flash interface with boot feature |
AMBA Bus
Operating Frequency
|
AMBA AHB bus: Up to 200 MHz |
| AMBA APB bus: Up to 100 MHz |
| H.264 Codec |
Supports the baseline profile encoding up to half duplex D1 at 120 fps. The resolution
is up to 1920x1280 at 20 fps stepped in units of 16 |
Supports the baseline profile decoding up to half duplex D1 at 60 fps. The resolution is
up to 1920x1280 at 10 fps stepped in units of 16 |
| Supports the baseline profile full duplex D1 at 60 fps. The resolution is up to 1920x1280 at 10 fps stepped in units of 16 |
| MPEG-4/JPEG Codec |
Supports MPEG4 simple profile encoding up to D1 @ 60 fps. The resolution is up to
1920x1280 @ 10 fps stepped in the units of 16 |
Supports MPEG4 simple profile decoding up to D1 @ 60 fps. The resolution is up to
1920x1280 @ 10 fps stepped in the units of 16
JPEG is compliant with ISO/IEC 10918-1 baseline standard |
| Video Capture |
users to paste any characters on the captured video. The features include:
Support a maximum input capture resolution of up to 1920 x 1080 |
| Supports four ITU 8-bit/16-bit 656 YUV 4:2:2 NTSC/PAL video inputs I/F up to 74.25 MHz |
| Supports four ITU 8-bit/16-bit 656 YUV 4:2:2 VGA/SXGA progressive inputs I/F up to 74.25 MHz |
| Supports one ITU-R BT.1120 format of 16-bit video input I/F |
| Supports SONY 16-bit YUV parallel input I/F |
| Supports RGB 888/RGB 565/YCbCr 4:4:4/YCbCr 4:2:2/YCbCr 4:2:0 output image formats |
| Supports edge-base line in average de-interlace |
| Individual image size-down at preview and record paths |
| Supports noise reduction function |
| Supports individual frame skip function at preview and record paths |
| Supports individual color OSD for preview and record paths |
| Source and output image crop |
| Adds borders at output Image |
| Implements up to 4000 x 4000 resolutions by combining the preview and record paths |
| Supports loop-back path to read image data through AHB from memory |
| Auto-loads VBI data to memory for software reading |
| Display Interface |
The LCDC block is a LCD controller that used to obtain the video data from the frame buffer and output to provide all the necessary control signals for various TFT LCD panels. The features of LCDC include: |
| Supports TFT color display with up to 24-bit bus interfaces |
| Programmable resolution of up to 1920 x 1080 |
| Pixel clock rate of up to 120 MHz |
Programmable polarity and duration for the output enable, veritical sync.,
horizontal sync, and pixel clock |
Programmable constrast, brightness, sharpness (Not supported for TV output),
saturation and hue control |
Picture-in-Picture (PiP)
- Supports a maximum of two PIP windows display
- Supports PiP window resolution similar to main window
- Supports 4-bit global blending levels
- Supports ARGB (5888) for each image |
| Supports 4-in-1 PoP window display |
On-Screen Display (OSD)
- RAM-based programmable 12x16 and font variety of up to 256
- Supports a maximal window font number of 512 and programmable window position
- Supports up-scaling function with factors 1, 2, 3, and 4
- Transparency type: 25%, 50%, 75%, and 100%
- 4-entry, 8-bit color palette for foreground
- 3-entry, 8-bit color palette for background (One entry reserved for transparency) |
| Programmable 12x16 hardware cursor |
| PCI Interface |
Compliant with PCI 2.2 specification |
| Supports the PCI bus clock rate up to 66 MHz |
| PCI bus supports 32-bit data bus transactions |
| Supports I/O read/write, memory read/write, and configuration read/write commands |
Supports the parity generation, parity error detection, target abort, target retry, and
master abort functions. |
| Supports the type 0 configuration space header |
| Supports the bus transaction ordering |
| Supports the PCI power management |
Giga Ethernet Controller (GMAC) |
The Giga Ethernet Controller (GMAC) blcok is a high-quality Ethernet controller with
the DMA function. |
| It includes the AHB wrapper, DMA engine, on-chip memories (TX FIFO and RX FIFO), MAC, and MII/GMII/RMII interfaces. |
AES/DES/3DES
Cipher
Controller |
DES/Triple-DES encryption/decryption compliant with NIST standard |
| AES 128/192/256-bit encryption/decryption compliant with NIST standard |
| Block cipher mode supports |
| AHB
Peripherals |
DDR2DDR2 SDRAM controller x 3 |
| Static memory controller |
| DMA controller |
| USB 2.0 OTG controller |
| Video capture x 4 |
| LCD controller x 2 |
| H.264 encoder |
| H.264 decoder |
| MPEG4/JPEG codec |
| AES/DES/3DES cipher controller |
| Ethernet MAC controller |
| PCI bridge |
| IDE controller |
| Scalar x 2 |
| NAND Flash controller |
| APB Peripherals |
Timer |
| Watch Dog timer |
| Interrupt controller |
| GPIO |
| I2C |
| SPI/I2S |
| I2S/AC97 |
| Full-function UART x 1 + Console UART x 1 (Or Console UART x 5) |
| Multimedia card 4.1/Secure Digital host controller 2.0/SDIO |
| Operating Voltage |
1.2 V for the core |
| 3.3 V for the input/output with 5 V tolerance |
| 1.8 V for the DDR DRAM I/O |
| Process |
UMC 0.13 μm logic process |
| Package |
PBGA700-35x35-01EA |
High advanced Mega-pixel IP camera