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| Andes Technology Corporation |
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| Andes Technology is located in Taiwan's Hsinchu Science Park and was established in 2005.
It is equipped with the SoC architecture technology and development and verification environment technology that includes the high-performance low-power 32-bit RISC processors and the audio DSP and is providing the total solution needed for customers in need of the SoC platform-based CPU design so that they can easily implement it with their specifications.
Furthermore, the ESL-based verification and the seamless SoC solution are available so that the customer can select and use the right development environment, and the innovative configurable CPU technology of Andes Technology is providing the optimal solution satisfying the various application specifications of customers.
The S/W and H/W configurability and extendability technology in the verified platform assist the customer in manufacturing optimized products and makes the time-to-market development of products possible. |
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AndeStar is the16-bit/32-bit mixed-length instruction set and includes the following features.
 Intermixable 32-bit and 16-bit instruction sets without the need for mode switch
- 16-bit instructions as a frequently used subset of 32-bit instructions
- RISC-style register-based instruction set
- 32 32-bit General Purpose Registers (GPR)
- Upto 1024 User Special Registers (USR) for existing and extension instructions
- Rich load/store instructions for
: Single memory access with base address update
: Multiple aligned and unaligned memory accesses for memory copy and stack operations
: Data prefetch to improve data cache performance
: Non-bus locking synchronization instructions
- PC relative jump and PC read instructions for efficient position independent code
- Multiply-add and multiple-sub with 64-bit accumulator
- Instruction for efficient power management
- Bi-endian support
- Three instruction extension space for application acceleration :
: Performance extension
: Andes future extensions (for floating-point, multimedia, etc.)
: Customer extensions |
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| Andes is providing 3 CPU core families to satisfy various embedded system applications. |
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| N12 : Linux 기반의 high-end application용 CPU Core |
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| Core's Features |
N1213 |
ARM1176 |
MIPS 24K |
| Instruction Set |
16-/32-bit mixable |
16or32 |
16 or 32 |
| General-purpose register# |
32 |
16 |
32 |
| Page Table Support for MMU |
HW and SW |
HW only |
SW only |
| Interrupt Stack Level |
3 |
2 |
1 |
| unaligned memory access |
ld/st multiple |
mode bit |
ld/st left/right |
| uncached read burst |
use ld multiple |
none |
none |
| DMA support |
1D/2D |
1D |
No |
| Core die size(mm2) |
1.38 |
1.95/1.00 |
*1.44 |
| Frequency(MHz) |
580 |
620/320 |
*520 |
| Power per MHz(mW/MHz) |
0.27 |
0.37/0.18 |
*0.40 |
| Dhrystone MIPS(DMIPS) |
795 |
756/390 |
*748 |
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| N10: The CPU core for the Linux and RTOS-based mid-range application |
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| Core's Features |
N1033A |
ARM926EJ |
| Pipeline Stages |
5 |
5 |
| Instruction Set |
16-/32-bit mixable |
16 or 32 |
| General-purpose register# |
32 |
16 |
| Dynamic branch prediction |
32/64/128-entry BTB |
No |
| DMA support |
1D and 2D |
No |
| Cache tag index |
Physical tag |
Virtual tag |
| Data endian support |
Big and Little |
Big and Little |
| MMU/MPU |
MMU or MPU |
MMU |
| Vectored interrupt support |
Yes(64 addresses) |
No |
| Nested interruption level |
3 |
No |
| Bus |
AHB/2AHB/AHB-Lite/APB |
2AHB |
| Audio DSP instructions |
>40 dedicated |
Few general DSP |
| Frequency(MHz) |
*250 |
250 |
| Dhrystone MIPS/Mhz |
*1.64 |
1.1 |
| Core die size(mm2) |
*1.70 |
1.68 |
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| N9 : CPU for the MCU-based low-end application |
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| Core's Features |
N903 |
ARM7TDMI |
Cortex-M3 |
| Instruction Set |
16-/32-bit mixable |
Thumb/ARM |
16-/32-bit mixable |
| General-purpose register # |
16 |
16 |
16 |
| Branch prediction |
Static |
None |
Static |
| *1st Interrupt latency (Cycle) |
9 |
24-42 |
12 |
| *Back-to Back |
7 |
24 |
6 |
| Bus |
APB/AHB/AHB-Lite |
1AHB |
3AHB Lite |
| Vectored interrupt support |
Yes |
None |
Yes |
| Cache configuration(KB) |
0~32 |
None |
None |
| DMIPS/MHz |
1.3 |
0.95 |
1.25 |
| Core Area(mm2)(TSMC0.13G) |
**0.62/0.47 |
0.35/0.24 |
0.74/0.38 |
| Frequency@TSMC0.13G(MHz) |
**212/100 |
184/106 |
135/50 |
| Power consumption(mw/Mhz) |
**0.038/0.036 |
0.18/0.10 |
0.165/0.084 |
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| Andes provides the SoC platform for embedded systems, and AG101P is the SoC platform IP used together with the AndesCore processor.
Users can easily attach the IPs needed for a specific application SoC to the system bus.
Users can verify the system performance and find out problems on the basis of the various simulation and design environment. |
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| AndeSight™ and AndESLive™ supports the Andes CPU-based SoC software development.
AndeSight™ is the Eclipse-based development suite and provides the effective embedded application development environment of a target system.
AndESLive™ is the ESL-based SoC verification tool and includes the SoC builder, models of CPU, peripherals, bus, and external devices (LCD panel, audio speaker, etc.). |
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| Andes is providing various kinds of software including OS/RTOS, application library, and middleware. |
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